As is well known in the field, the parameter c.f noise immunity is important in ensuring the stable operation of modern integrated circuits. Since the magnitude of noise from parasitic inductance of a conductive line increases with the switching speed of signals carried thereon, the noise immunity of a circuit has become more problematic in recent years, considering that the switching frequencies of digital integrated circuits has increased to on the order of tens of MHz. The design of input buffers for modern integrated circuits, such input buffers for receiving signals from conductors external to the circuit, has thus become crucial in assuring acceptable noise immunity characteristics for the circuit at such frequencies.
A conventional approach to providing noise immunity for input buffers of integrated circuits is to provide hysteresis in the transfer characteristic of the buffer. As is fundamental in the art, hysteresis in the transfer characteristic means that the switching threshold voltage of a circuit depends upon the polarity of the excursion at the input, so that the threshold voltage for switching the buffer is offset from the threshold voltage for switching back to the prior state. For example, a conventional buffer may have a threshold voltage of 2.0 volts for switching from a "0" to a "1" state, but a threshold voltage of 0.8 volts for switching from a "1" to a "0" state; 1.2 volts of noise immunity is thus provided.
Referring to FIG. 1, conventional CMOS input buffer 1 with a hysteresis characteristic is illustrated. Pad 8 is the bond pad which receives the signal from external to the integrated circuit in which buffer 1 is implemented. A first stage of buffer 1 is a CMOS inverter formed by p-channel pull-up drive transistor 2p and n-channel pull-down drive transistor 2n, which have their source-drain paths connected in series between the V.sub.cc power supply and ground, and which have their gates connected to pad 8. It is to be noted that conventional electrostatic discharge protection devices may be connected in series with or in parallel to the connection between pad 8 and drive transistors 2p, 2n, in the conventional manner. The drains of drive transistors 2p, 2n are connected to the input of inverter 3, which drives node N at its output. Node N is communicated to the remainder of the integrated circuit in the conventional manner, so that the signal received at pad 8 is processed thereby.
In conventional "TTU" compatible input circuits, the nominal switching threshold voltage of the inverter of drive transistors 2 is preferably 1.4 volts (midway between the standard VIH/VIL levels of 2.0 volts and 0.8 volts, respectively). As a result, drive transistors 2n, 2p are heavily ratioed relative to one another. For example, drive transistor 2n may have a width/length (W/L) ratio of approximately 3 to 5 times that of drive transistor 2p, to provide a drive strength of 6 to 10 times that of drive transistor 2p (considering the mobility difference between p-channel and n-channel transistors).
Hysteresis for the low-to-high transition at pad 8 is provided by p-channel transistor 4p, having its source-drain path connected between the input of inverter 3 and V.sub.cc, and having its gate connected to node N at the output of inverter 3. Conversely, hysteresis for the high-to-low transition at pad 8 is provided by n-channel transistor 4n, which has its source-drain path connected between the input of inverter 3 and ground, and which has its gate also connected to node N at the output of inverter 3.
In operation, one of hysteresis transistors 4 will be turned on by inverter 3 according to the prior logic state at pad 8, and will oppose the switching of the input of inverter 3 by the one of drive transistors 2 that is turned on by the new logic level at pad 8. For example, if the previous logic state at pad 8 is a "0", drive transistor 2p is on and pulls the input of inverter 3 high. This causes a low level at node N, turning on hysteresis transistor 4p. In this example, if pad 8 then is driven low, drive transistor 2n turns on, and begins to pull the input of inverter 3 low. Since hysteresis transistor 4p remains on until inverter 3 switches, the current sourced by hysteresis transistor 4p will oppose the action of drive transistor 2n in pulling the input of inverter 3 low.
Accordingly, as is well known, the hysteresis of input buffer 1 is determined by the difference in the drive characteristics of drive transistors 2p, 2n relative to their respective opposing hysteresis transistors 4n, 4p. If the drive of an hysteresis transistor 4 approaches the drive of its respective opposing drive transistor 2, the magnitude of hysteresis will be quite large; conversely, the hysteresis magnitude will become weaker as the relative drive capability of hysteresis transistor 4 relative to its opposing drive transistor 2 becomes weaker. Proper selection of the hysteresis characteristics of the buffer generally requires that the drive of hysteresis transistors 4 must be much weaker than that of drive transistors 2. As such, in conventional buffers such as buffer 1, hysteresis transistors 4 are conventional fabricated to have much lower W/L ratios than those of drive transistors 2. For example, where the W/L ratio of drive transistor 2n is 20, a typical W/L ratio for hysteresis transistor 4p is 4.0; conversely, where drive transistor 2p has a W/L ratio of 4.6, a typical value of W/L for hysteresis transistor 4n may be 0.4.
Especially in modern high speed integrated circuits using sub-micron minimum feature sizes, there are limits to achieving small W/L ratios for hysteresis transistors 4. Firstly, limits exist beyond which the channel width W for hysteresis transistors 4 may be reduced. This is due to small width effects that begin as channel widths are reduced to on the order of three microns. Since the channel width W of drive transistors 2 will generally be quite large to effect rapid switching (e.g., on the order of four to five microns), extremely short channel widths W for hysteresis within the region at which small width effects are present, will result in tracking problems between hysteresis transistors 4 and their opposing drive transistors 2. As such, reduction of the W/L ratio for hysteresis transistors 4 can only in small part be accomplished by reduction of the channel width W, and as such the channel length L of hysteresis transistors 4 must be increased to meet the desired transfer characteristic. For example, for a safe channel width of 4.0 microns in a 0.7 micron minimum feature size process, the channel length L of hysteresis transistors 4 may have to be increased to ten to fifteen times that of drive transistors 2 (i.e., channel length on the order of six to ten microns).
Increase in the channel length L of hysteresis transistors 4 also has limitations, however. Firstly, as the channel length L of hysteresis transistors 4 increases, the gate-to-source capacitive load on inverter 3 at node N greatly increases, slowing the switching characteristics of buffer 1. Additional delays of on the order of 0.2 to 0.5 nsec due to such sizing of hysteresis transistors 4 have been observed; such additional delays are quite significant for circuits such as high-speed static RAMs. In addition, as the channel length L of hysteresis transistors 4 is made significantly larger than that of drive transistors 2, short channel effects are much reduced for hysteresis transistors 4. As a result, normal process variations, such as critical dimension (CD) variations, will non-uniformly affect drive transistors 2 and their opposing hysteresis transistors 4, creating physical mismatch conditions for some locations in the process window. As noted above, the relative drive characteristics between drive transistors 2 and their opposing hysteresis transistors 4 is critical in determining the operation of buffer 1, making such physical mismatch conditions as a function of process directly affect circuit performance. As such, the use of large channel length hysteresis transistors 4 provides poor process tolerance for important circuit parameters such as input buffer switching.
It is therefore an object of the present invention to provide an input buffer circuit with hysteresis characteristics with reduced delay characteristics.
It is a further object of the present invention to provide such an input buffer circuit with improved process tolerance.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.